1. Field of the Invention
The present invention relates to a reactive power compensation device, and more particularly to a thyristor switch gate pulse generator for capacitor load switching in a reactive power compensation device.
2. Discussion of the Background
In the past, the main demand for reactive power compensation devices has been for flicker control of arc furnaces and rolling mills, but in recent years there has also been interest in their applications for changing power system voltages and power surge control, etc. and they are also coming into increased use in transformer substation filter phase advancing equipment. Such equipment uses a combination of TCRs (thyristor controlled reactors) for which normally reactor current is controlled by thyristors or thyristor switches (thyristor switched capacitors; referred to below as TSCs) which have thyristor converters connected in series to capacitors and reactors.
Increases in the voltage and capacity of such equipment have involved the use of TCRs constituted by series connections of large numbers of thyristors. Since the load of a TSC is a capacitor, it functions as an on-off switch and a gate pulse generator that switches the thyristors on and off must be able to switch a large number of thyristors on and off all together at high speed.
The prior art will now be described with reference to FIGS. 3, 4, 5, 6A and 6B.
FIG. 3 is a block diagram of a typical TSC. A capacitor 2, a reactor 4 and a thyristor converter 8 constituted by a gate pulse generator 6 which produces gate pulse signals for thyristors 3U and 3X in response to on-off commands from a control unit 7 are connected in series to a TSC transformer 1.
Reference numeral 5 designates a circuit for detection of thyristor switch 3U and 3X voltage.
FIG. 4 shows the waveforms during normal operation of the various sections of the TSC shown in FIG. 3. VS is the primary voltage of the TSC transformer and IC and VC are the current and voltage of the capacitor constituting the load of the thyristor converter.
PHS indicates phase control signals (referred to below as PHS) which are output by control unit 7 and are produced at the peak phase of power supply voltage VS to make the TSC converter excitation rush current minimum.
Mostly in recent years, a narrow gate pulse system has been employed for thyristor gate pulse generation. A narrow gate pulse system is one in which triggering signals in the form of one-shot pulses are supplied to thyristors at thyristor triggering times and compared to a conventional broad pulse system. It has the advantage that it is possible to make the power supply circuit of the gate pulse generator smaller and cheaper, etc.
FIG. 5 shows a gate pulse generator in a narrow gate pulse system. Reference numerals 8U and 8X designate flip-flop circuits, 9U and 9X AND gates, 10U and 10X one-shot circuits that output set pulse widths, 11U and 11X OR gates, 12 a one-shot circuit, 13 an AND gate, 14 a time delay circuit that outputs a signal after a set delay, 15 an AND gate and 16 a time delay circuit.
Flip-flop circuit 8U is set by a PHS(U) pulse output by the control circuit 7. A gate pulse signal GP(U) (referred to as GP below) of set width is output by one-shot circuit 10U and supplied to a gate of a thyristor switch only when the logical product of the forward voltage signal FV(U) of thyristor 3U and the Q output of flip flop 8U at AND gate 9U is "1".
Flip-flop circuit 8U that has been set by a PHS(U) pulse is reset by the logical sum output of OR gate 11U.
For one input of OR gate 11U, while one-shot circuit 12 is outputting a set pulse width after output of a gate pulse signal GP(X) of opposite-phase thyristor 3X, the logical product taken by AND gate 13 shows that both the forward voltage signal FV(U) of thyristor switch 3U and the F signal FV(X) of thyristor switch 3X (a reverse voltage signal with respect to reactor 4 of thyristor switch 3U) are "0" and this logical product becomes "1" only when time delay circuit 14 causes continuation for more than a set time.
In other words, the output of time delay circuit 14 becomes "1" only if a state in which both the forward voltage signal FV(U) and the reverse voltage signal FV(X) are not present in a set time after supply of a gate pulse signal GP(X) to opposite-phase thyristor switch 3X has continued for more than the thyristor turn-off time.
Output signals of time delay circuit 16 are supplied to the other input of OR gate 11U.
The logical product of GB signals (system stop signals) and reverse voltage signals FV(X) is taken at AND gate 15 and the output of this logical product becomes "1" only after time delay circuit 16 has caused continuation for more than a set time.
In other words, the output of time delay circuit 16 becomes "1" when a reverse voltage is imposed for more than the turn-off time after stopping.
Gate pulses GP(U) are output while setting of flip-flop circuit 8U by PHS(U) pulses and resetting of 8U by the two types of signals described above are alternately repeated.
Generally speaking, there are no problems with the above-described gate pulse generator resetting method as long as there is no need to consider external factors such as system voltage surges, etc. but since in actual fact external factors too must be taken into consideration, a problem as explained in relation to FIGS. 6A, 6B and 6C occurs.
FIG. 6A is a waveform timing diagram showing waveforms during the TSC operation, and particularly illustrates the TSC converter 1 secondary side voltage VS, capacitor current and voltage IC and VC, the voltage V.sub.A-K across opposite electrodes of thyristor switch 3U and the forward side and reverse side gate pulse signals GP(U) and GP(X). The waveforms of FIG. 6A are representative of normal operation of the circuit shown in FIG. 5.
FIG. 6B illustrates operation of the circuit shown in FIG. 5 in the case where an intermittence of current occurs. In particular, the particular waveforms shown in FIG. 6B illustrate the case where the capacitor current IC is made intermittent by a system voltage surge. When the capacitor current is intermittent, the AND condition of 9U (or 9X) is established and GPs of both phases are output out of synchronism with the PHS signals and protection against partial commutation failure of thyristor switches 3U and 3X is effected. If, subsequently, the intermittency of the current comes to an end and there is a move to normal conduction, the conditions for the resetting circuits of flip-flops 8U and 8X are established and so the flip-flops of both phases are reset.
In FIG. 6B, when U phase conduction ends and there is a move to X phase conduction, the current is intermittent and after a set time both the flip-flops are reset.
Action by the resetting circuit of flip-flop 8U is a correct action but since flip-flop 8X is reset soon after own-phase conduction starts, GP output becomes impossible even if the current is intermittent when X phase conduction ends and therefore partial commutation failure is caused and one can anticipate breakdown of thyristor elements.
Next described in more detail in relation to the waveform shown in FIG. 6B is a mechanism by which partial commutation failure occurs. In FIG. 6B, two intermittences occur at t2 and t7. Flip-flop 8X is reset at time t5, which is delayed from t2 by the delay time Td. The prior art circuit shown in FIG. 5 has the problem that if a second intermittence occurs at t7 and terminates at t8, GP(X) cannot be generated. GP(X) can be generated when the state of F.F.(U) is "1". As the state of F.F.(U) is "0" at t8 (see FIG. 6B), GP(X) cannot be generated at t8. The thyristor 3X is turned off at t7 because the reverse voltage is applied to the thyristor 3X. The forward voltage is applied to the thyristor 3X at t8, and some elements of the thyristor 3X may turn on and other elements may not turn on. A partial commutation failure may occur due to differences in the characteristics of the thyristor elements when the forward voltage is applied to the thyristor before the turn-off time. Partial commutation failure occurs in the absence of GP(X) due to the characteristics of thyristors connected in series. In series connection, there is a dispersion in turn-off time of the series connected thyristors. Each thyristor has its own turn-off time. In general, if a positive voltage is applied to a thyristor in a short time after turn-off, the thyristor turns on in the absence of a gate pulse. If the positive voltage is applied at the point after "turn-off time", the thyristors do not turn on in the absence of a gate pulse.
For example, if the time of applying a negative voltage T has the value as defined by the following relationship, partial commutation failure occurs: EQU Tmin&lt;T&lt;Tmax,
where Tmin refers to the minimum turn-off time of the thyristors and Tmax refers to the maximum turn-off time of the thyristors. In this case, some elements are turned on and the other elements are maintained in the off condition, which results in a partial commutation failure condition. If a small number of thyristors, such as, only one thyristor is in the off condition, the total voltage is then applied to that one thyristor thereby destroying that thyristor.
In the circuit of FIG. 5, the delay time Td of the delay timer 14 is set so that Td is greater than the turn-off time of the thyristor. F.F.(U) is reset at t6 by GP(U) after a time delay Td after t2.
The possibility of partial commutation failure in the conventional circuit of FIG. 5 is a very great drawback from the point of view of providing a highly reliable reactive power compensation device.